| Classification Of Sip Attack Variants With A Hybrid Self-Enforcing Network | 0 | 0.34 | 2018 |
| Application of Visual Analysis to Detect and Analyze Patterns in VoIP Attack Traffic | 0 | 0.34 | 2018 |
| A distributed infrastructure to analyse SIP attacks in the Internet | 4 | 0.49 | 2014 |
| Development and Analysis of Generic VoIP Attack Sequences Based on Analysis of Real Attack Traffic | 0 | 0.34 | 2013 |
| TuneLogic: Post-silicon tuning of dual-Vdd designs | 1 | 0.36 | 2009 |
| TuneFPGA: post-silicon tuning of dual-Vdd FPGAs | 3 | 0.46 | 2008 |
| Optimal constraint-preserving netlist simplification | 7 | 0.50 | 2008 |
| A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions | 4 | 0.58 | 2007 |
| Sequential Circuits for Relational Analysis | 5 | 0.43 | 2007 |
| Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations | 22 | 0.91 | 2007 |
| Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies | 0 | 0.34 | 2007 |
| Sequential circuits for program analysis | 1 | 0.35 | 2007 |
| The hazard-free superscalar pipeline fast fourier transform algorithm and architecture | 1 | 0.40 | 2007 |
| Implementing DSP Algorithms with On-Chip Networks | 0 | 0.34 | 2007 |
| Global Optimization of Compositional Systems | 0 | 0.34 | 2007 |
| Cache Organization For Embeded Processors: Cam-Vs-Sram | 3 | 0.48 | 2006 |
| Scheduling Traffic Matrices On General Switch Fabrics | 2 | 0.47 | 2006 |
| Exploiting constraints in transformation-based verification | 7 | 0.50 | 2005 |
| Scalable compositional minimization via static analysis | 6 | 0.44 | 2005 |
| Simplifying Boolean constraint solving for random simulation-vector generation | 24 | 1.10 | 2004 |
| Synthesizing interconnect-efficient low density parity check codes | 7 | 0.57 | 2004 |
| Randomized parallel schedulers for switch-memory-switch routers: analysis and numerical studies | 17 | 0.86 | 2004 |
| Towards Automating an Interventional Radiology Procedure | 2 | 0.65 | 2004 |
| An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists | 9 | 0.89 | 2003 |
| Sequential optimization in the absence of global reset | 1 | 0.37 | 2003 |
| Constraint synthesis for environment modeling in functional verification | 16 | 1.01 | 2003 |
| A Framework for Constrained Functional Verification | 20 | 1.11 | 2003 |
| A near optimal scheduler for switch-memory-switch routers | 12 | 0.82 | 2003 |
| A Reconfigurable Architecture and Associated Synthesis Methodology for High Speed Packet Classification | 0 | 0.34 | 2002 |
| A Middle Ground between CAMs and DAGs for High-Speed Packet Classification | 0 | 0.34 | 2002 |
| Simplifying Constraint Solving in Random Simulation Generation | 0 | 0.34 | 2002 |
| An O(log2N) parallel algorithm for output queuing | 8 | 0.64 | 2002 |
| Improved SAT-based Bounded Reachability Analysis | 18 | 1.05 | 2002 |
| Multicast Scheduling for Switches with Multiple Input-Queues | 18 | 1.22 | 2002 |
| A Method for Synthesizing Boolean Constrains | 0 | 0.34 | 2002 |
| OC-3072 packet classification using BDDs and pipelined SRAMs. | 4 | 0.91 | 2001 |
| Integrated power supply planning and floorplanning | 13 | 1.05 | 2001 |
| Rarity based guided state space search | 7 | 0.52 | 2001 |
| SIVA: A System for Coverage-Directed State Space Search | 9 | 0.71 | 2001 |
| Theory of safe replacements for sequential circuits | 11 | 0.69 | 2001 |
| Efficient control state-space search | 1 | 0.36 | 2001 |
| Optimizing designs containing black boxes | 0 | 0.34 | 2001 |
| Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing | 0 | 0.34 | 2000 |
| Model-checking continuous-time Markov chains | 248 | 10.09 | 2000 |
| Automatic Vector Generation Using Constraints and Biasing | 2 | 0.62 | 2000 |
| Simultaneous Routing And Buffer Insertion With Restrictions On Buffer Locations | 5 | 0.59 | 2000 |
| Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion | 38 | 1.86 | 2000 |
| Automatic lighthouse generation for directed state space search | 8 | 0.55 | 2000 |
| Sequential synthesis using S1S | 14 | 1.01 | 2000 |
| An Abstraction Algorithm for the Verification of Generalized C-Slow Designs | 8 | 1.02 | 2000 |
