Name
Abstract | ||
|---|---|---|
Image processing applications tend to access their data non-sequentially and reuse that data infrequently. As a result, they tend to perform poorly on conventional memory systems due to high cache and TLB miss rates and are particularly sensitive to the growing latency of main memory. We analyze the memory performance of three image processing algorithms (volume rendering, image warping and image filtering) on both a conventional memory system and on the Impulse memory system. The Impulse memory system allows application software to control how, when, and where data are loaded into a conventional processor cache. It does this by letting software configure how the memory controller interprets the physical addresses exported by the processor, which enables an application to dynamically change how data are fetched. Sparse data can be accessed densely, which improves both cache and TLB utilization, and memory latency is hidden by prefetching data within the memory controller. We find that for these image processing codes, using an Impulse memory system yields speedups of 40% to 226% over an otherwise identical machine with a conventional memory system |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/PACT.1999.807426 | IEEE PACT |
Keywords | Field | DocType |
prefetching,impulse memory system yield,image processing,image warping,cache storage,memory latency,latency,volume rendering,main memory,memory controller,virtual memory,conventional memory system,impulse memory system,memory performance,image filtering,memory architecture,performance evaluation,memory bandwidth,prefetching data,memory system support,tlb miss rates,bus utilization,cache efficiency,cache memory,data infrequently,data non-sequentially,image analysis,algorithms,application software,sparse data,control systems,yield,velocity,algorithm design and analysis,computer applications,control,addressing | Registered memory,Semiconductor memory,Interleaved memory,Uniform memory access,Computer science,Parallel computing,Cache-only memory architecture,Real-time computing,Memory map,Computer hardware,Memory segmentation,Computer memory | Conference |
ISSN | ISBN | Citations |
1089-795X | 0-7695-0425-6 | 9 |
PageRank | References | Authors |
0.78 | 17 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lixin Zhang | 1 | 571 | 45.96 |
| John B. Carter | 2 | 1785 | 162.82 |
| Wilson C. Hsieh | 3 | 2532 | 261.94 |
| Sally A. Mckee | 4 | 1928 | 152.59 |