Paper Info
Title
Area/performance trade-off analysis of an FPGA digit-serial GF(2m) Montgomery multiplier based on LFSR
Abstract
Montgomery Multiplication is a common and important algorithm for improving the efficiency of public key cryptographic algorithms, like RSA and Elliptic Curve Cryptography (ECC). A natural choice for implementing this time consuming multiplication defined on finite fields, mainly over GF(2^m), is the use of Field Programmable Gate Arrays (FPGAs) for being reconfigurable, flexible and physically secure devices. FPGAs allow the implementation of this kind of algorithms in a broad range of applications with different area-performance requirements. In this paper, we explore alternative architectures for constructing GF(2^m) digit-serial Montgomery multipliers on FPGAs based on Linear Feedback Shift Registers (LFSRs) and study their area-performance trade-offs. Different Montgomery multipliers were implemented using several digits and finite fields to compare their performance metrics such as area, memory, latency, clocking frequency and throughput to show suitable configurations for ECC implementations using NIST recommended parameters. The results achieved show a notable improvement against FPGA Montgomery multiplier previously reported, achieving the highest throughput and the best efficiency.
Year
DOI
Venue
2013
10.1016/j.compeleceng.2012.08.010
Computers and Electrical Engineering
Keywords
DocType
Volume
performance trade-off analysis,fpga digit-serial gf,area-performance trade-offs,digit-serial montgomery multiplier,different area-performance requirement,highest throughput,finite field,best efficiency,different montgomery multiplier,montgomery multiplication,elliptic curve cryptography,fpga montgomery multiplier
Journal
39
Issue
ISSN
Citations 
2
0045-7906
8
PageRank 
References 
Authors
0.50
13
4
Name
Order
Citations
PageRank
Miguel Morales-Sandoval110921.53
Claudia Feregrino-Uribe214118.92
P. Kitsos313015.47
René Cumplido417129.56