P. Kitsos - Citegraph

Author Info

Name	Affiliation	Papers
P. KITSOS	Dept. of Electr. & Comput. Eng., Patras Univ., Greece	16
Collaborators	Citations	PageRank
23	130	15.47
Referers	Referees	References
296	217	113

Search Limit

100296

Publications (16 rows)

Collaborators (23 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Area/performance trade-off analysis of an FPGA digit-serial GF(2m) Montgomery multiplier based on LFSR	8	0.50	2013
VLSI Design and Implementation of Homophonic Security System	1	0.43	2012
Architectural Optimizations & Hardware Implementations of WLANs Encryption Standard	0	0.34	2012
Snmp for Ethernet Networks SETH: A Network Benchmark Toolkit for Managing Routers Statistical Information	2	0.39	2011
Bit-serial and digit-serial GF(2m)Montgomery multipliers using linear feedback shift registers.	14	0.80	2011
Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security	3	0.84	2006
Cryptography: circuits and systems approach	3	0.48	2005
64-bit Block ciphers: hardware implementations and comparison analysis	9	0.68	2004
Efficient architecture and hardware implementation of the Whirlpool hash function	10	0.96	2004
Comparison of the hardware architectures and FPGA implementations of stream ciphers	14	1.19	2004
VLSI implementations of the triple-DES block cipher.	2	0.46	2003
An efficient reconfigurable multiplier architecture for Galois field GF(2m)	34	1.78	2003
An reconfigurable multiplier in GF(2m) for elliptic curve cryptosystem	2	0.36	2003
Hardware Implementation of Bluetooth Security	15	2.00	2003
Random number generator architecture and VLSI implementation	13	3.92	2002
Hardware implementation of the SAFER+ encryption algorithm for the Bluetooth system	0	0.34	2002

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