Name
Abstract | ||
|---|---|---|
Partial scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several techniques for flip-flop selection based on structural analysis have been presented in the literature. In this paper we first propose a new testability measure based on the analysis of the circuit State Transition Graph (STG) through symbolic techniques. We then describe a scan flip flop selection algorithm exploiting this measure. We resort to the identification of several circuit macros to address large sequential circuits. When compared to other techniques, our approach shows good results, especially when it is used to optimize a set of flip-flops previously selected by means of structural analysis |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/DATE.1998.655930 | Paris |
Keywords | Field | DocType |
circuit macro,partial scan technique,symbolic technique,flip-flop selection,flip flop selection algorithm,new testability measure,sequential atpg performance,large sequential circuit,structural analysis,performance overhead,circuit state transition graph,routing,automatic test pattern generation,sequential analysis,graph theory,sequential circuits,design for testability,tellurium,structure analysis | Testability,Graph theory,Design for testing,Automatic test pattern generation,Sequential logic,Computer science,Selection algorithm,Algorithm,Real-time computing,Flip-flop,Macro | Conference |
ISBN | Citations | PageRank |
0-8186-8359-7 | 4 | 0.45 |
References | Authors | |
9 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| F. Corno | 1 | 602 | 55.65 |
| P. Prinetto | 2 | 516 | 55.23 |
| M. Sonza Reorda | 3 | 1099 | 114.76 |
| Massimo Violante | 4 | 602 | 66.91 |