Paper Info
Title
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption
Abstract
In this paper, we propose a novel low power/energy Built-In Self Test (BIST) strategy based on circuit partitioning. The goal of the proposed strategy is to minimize the average power, the peak power and the energy consumption during pseudo-random testing without modifying the fault coverage. The strategy consists in partitioning the original circuit into two structural subcircuits so that each subcircuit can be successively tested through two different BIST sessions. In partitioning the circuit and planning the test session, the switching activity in a time interval (i.e. the average power) as well as the peak power consumption are minimized. Moreover, the total energy consumption during BIST is also reduced since the test length required to test the two subcircuits is roughly the same as the test length for the original circuit. Results on ISCAS circuits show that average power reduction of up to 72%, peak power reduction of up to 53%, and energy reduction of up to 84% can be achieved
Year
Venue
Keywords
1999
ATS '01 Proceedings of the 10th Anniversary Compendium of Papers from Asian Test Symposium 1992-2001
average power,minimized peak power consumption,low power bist design,peak power reduction,peak power,iscas circuit,novel low power,test session,test length,average power reduction,average powerreduction,circuit partitioning,peak power consumption,original circuit,low power electronics,packaging,test,system testing,fault coverage,vlsi,cmos technology,random testing
Field
DocType
ISBN
Fault coverage,Computer science,System testing,Real-time computing,CMOS,Electronic engineering,Electronic circuit,Energy consumption,Very-large-scale integration,Low-power electronics,Built-in self-test
Conference
0-7695-1233-x
Citations 
PageRank 
References 
33
2.08
12
Authors
4
Name
Order
Citations
PageRank
P. Girard147841.91
L. Guiller238024.24
C. Landrault3332.08
S. Pravossoudovitch468954.12