Name
Abstract | ||
|---|---|---|
A switch-level test generation system for synchronous and asynchronous circuits has been developed in which a new algorithm for fully automatic switch-level test generation and an existing fault simulator have been integrated. For test generation, a switch-level circuit is modeled as a logic network that correctly models the behavior of the switch-level including bidirectionality, dynamic charge storage, and ratioed logic. The algorithm is able to generate tests for combinational and sequential circuits. BothnMOS and CMOS circuits can be modeled. In addition to the classical line stuck-at faults, the algorithm is able to handle stuck-open and stuck-closed faults on the transistors of the circuit. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1007/BF00993130 | J. Electronic Testing |
Keywords | Field | DocType |
stuck-open and stuck-at faults,asynchronous circuit,automatic test generation,reverse time processing,time-frame expansion.,sequential circuits,switch-level test generation system | Stuck-at fault,Automatic test pattern generation,Sequential logic,Fault coverage,Computer science,Real-time computing,Electronic engineering,CMOS,Fault Simulator,Electronic circuit,Asynchronous circuit | Journal |
Volume | Issue | ISSN |
6 | 1 | 1573-0727 |
Citations | PageRank | References |
4 | 0.40 | 15 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kent L. Einspahr | 1 | 19 | 2.63 |
| Sharad C. Seth | 2 | 671 | 93.61 |