Name
Abstract | ||
|---|---|---|
A process, voltage, and temperature (PVT) variation conditioning technique using magnetic tunnel junction (MTJ) devices, whose resistance values are programmable, is proposed for realizing a wider design margin in analog integrated circuits. Because MTJ devices are fabricated on top of the CMOS integrated circuit layer, there is a small chip-area overhead for inserting additional MTJ devices into analog circuits, which makes it easy to use the variation-conditioning technique frequently on the entire chip. Additionally, the use of series-parallel connections for MTJ devices allows more flexible adjustment of the resistance. As a typical example, we demonstrate that under 0.18 mm CMOS technology, a simple operational Tran conductance amplifier (OTA) using the proposed technique outperforms a conventional OTA without any variation-conditioning technique. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISMVL.2012.52 | ISMVL |
Keywords | Field | DocType |
conventional ota,process-variation-resilient ota,analog circuit,mm cmos technology,mtj-based multi-level resistance control,proposed technique,variation-conditioning technique,variation conditioning technique,additional mtj device,analog integrated circuit,cmos integrated circuit layer,mtj device,magnetic tunnel junction,operational amplifiers,analog circuits,series parallel,resistance,operational transconductance amplifier,optimization,cmos integrated circuits,resistors,chip,process variation,very large scale integration | Analogue electronics,Computer science,Voltage,CMOS,Chip,Electronic engineering,Process variation,Integrated circuit,Electrical engineering,Operational amplifier,Amplifier | Conference |
ISSN | Citations | PageRank |
0195-623X | 2 | 0.44 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masanori Natsui | 1 | 80 | 15.10 |
| Takaaki Nagashima | 2 | 2 | 0.44 |
| Takahiro Hanyu | 3 | 441 | 78.58 |