Masanori Natsui - Citegraph

Author Info

Name	Affiliation	Papers
MASANORI NATSUI	Tohoku Univ, Elect Commun Res Inst, Aoba Ku, 2-1-1 Katahira, Sendai, Miyagi 9808577, Japan	34
Collaborators	Citations	PageRank
77	80	15.10
Referers	Referees	References
207	397	141

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100397

Publications (34 rows)

Collaborators (77 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator	0	0.34	2022
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition	0	0.34	2021
12.1 An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz	1	0.42	2019
Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks	1	0.37	2019
A 47.14-$\Mu\Text{W}$ 200-Mhz Mos/Mtj-Hybrid Nonvolatile Microcontroller Unit Embedding Stt-Mram And Fpga For Iot Applications	0	0.34	2019
Design of MTJ-Based nonvolatile logic gates for quantized neural networks.	1	0.37	2018
Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction	1	0.38	2018
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing.	5	0.52	2016
A study of a top-down error correction technique using Recurrent-Neural-Network-based learning	0	0.34	2016
Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission	0	0.34	2016
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction	12	0.65	2015
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm	4	0.42	2015
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure	8	0.51	2015
A Compact Low-Power Nonvolatile Flip-Flop Using Domain-Wall-Motion-Device-Based Single-Ended Structure	0	0.34	2014
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating	18	1.26	2013
Fabrication Of A Magnetic Tunnel Junction-Based 240-Tile Nonvolatile Field-Programmable Gate Array Chip Skipping Wasted Write Operations For Greedy Power-Reduced Logic Applications	9	1.06	2013
Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices.	2	0.43	2013
MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI	2	0.40	2013
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique.	0	0.34	2012
Process-Variation-Resilient OTA Using MTJ-based Multi-level Resistance Control	2	0.44	2012
Variation-Resilient Current-Mode Logic Circuit Design Using Mtj Devices	4	0.60	2012
Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology.	0	0.34	2011
Design Optimization Of High-Speed And Low-Power Operational Transconductance Amplifier Using G(M)/I-D Lookup Table Methodology	1	0.39	2011
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control	0	0.34	2010
Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using A Completion-Detection Scheme	2	0.50	2010
Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System	2	0.44	2009
Automated Sizing Of Analog Circuits Based On Genetic Algorithm With Parameter Orthogonalization Procedure	0	0.34	2008
Synthesis Of Current Mirrors Based On Evolutionary Graph Generation With Transmigration Capability	0	0.34	2007
Pitch Estimation Of Difficult Polyphony Sounds Overlapping Some Frequency Components	0	0.34	2006
Ga-Based Approach To Pitch Recognition Of Musical Consonance	0	0.34	2006
Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis.	2	0.45	2005
Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation	3	0.42	2004
Vlsi Circuit Design Using An Object-Oriented Framework Of Evolutionary Graph Generation System	0	0.34	2003
Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis	0	0.34	2002