Paper Info
Title
BIST TPG for Combinational Cluster Interconnect Testing at Board Level
Abstract
A novel built-in self-test (BIST) architecture and a test pattern generator (TPG) design methodology to program this architecture are presented for inter-IC interconnects among combinational non-boundary scan ICs (often called cluster-ICs) via IEEE 1149.1 boundary scan architecture (BSA). Due to the expense and complexity of BSA circuitry, cluster-ICs are still widely used in modern circuit boards. Since combinational logic and 3-state cluster nets exist within cluster interconnect, in order to test all detectable faults in inter-IC nets that include cluster-ICs, newly identified TPG requirements are used to guarantee fault coverage during the design of proposed BIST architecture. This architecture contains a two-level C-TPG that generates constrained pseudo-random patterns for boundary scan cells (BSCs) of cluster control cones, a D-TPG that generates patterns for BSCs of cluster data cones, and a look-up table which is programmed to select, for each BSC, a specific C-TPG or D-TPG stage whose content is shifted into that BSC. This test architecture provides a true BIST solution for cluster testing. The proposed methodology generates TPGs that (i) guarantee the avoidance of multi-driver conflicts when testing via BSA, (ii) guarantee the detection of all testable interconnect faults, (iii) have low area overheads, and (iv) have short test lengths.
Year
DOI
Venue
2000
10.1023/A:1008308430051
J. Electronic Testing
Keywords
Field
DocType
boundary scan,built-in self-test,BIST,cluster testing,interconnect testing
Boundary scan,Architecture,Fault coverage,Computer science,Printed circuit board,Combinational logic,Test pattern generators,Real-time computing,Interconnection,Embedded system,Built-in self-test
Journal
Volume
Issue
ISSN
16
5
1573-0727
Citations 
PageRank 
References 
1
0.42
9
Authors
2
Name
Order
Citations
PageRank
Chen-Huan Chiang1537.33
Sandeep K. Gupta21980229.01