Name
Abstract | ||
|---|---|---|
Mixed analog and digital mode simulators have been available for accurate transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. The authors describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. The simulation environment uses a timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses high level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The simulation environment is demonstrated on ISCAS-89 sequential benchmark circuits. |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1109/FTCS.1993.627334 | FTCS |
Keywords | Field | DocType |
sequential circuits,fault models,timing fault simulator,zero-delay parallel fault simulator,iscas-89 sequential benchmark circuits,high level models,gate-level transient fault simulation environment,latch outputs,latch operation,application software,analog computers,computational modeling,hardware | Stuck-at fault,Sequential logic,Fault coverage,Electronic engineering,Engineering,Fault Simulator,Electronic circuit,Fault indicator,Speedup | Conference |
ISSN | ISBN | Citations |
0731-3071 | 0-8186-3680-7 | 28 |
PageRank | References | Authors |
12.56 | 3 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hungse Cha | 1 | 112 | 24.74 |
| Elizabeth M. Rudnick | 2 | 867 | 76.37 |
| Gwan Choi | 3 | 369 | 56.66 |
| J. H. Patel | 4 | 4577 | 527.59 |
| Ravishankar K. Iyer | 5 | 3489 | 504.32 |