Name
Abstract | ||
|---|---|---|
An ADPLL with a piecewise linear calibrated hierarchical TDC is proposed to achieve a wide range of operation and a CPPLL is cascaded to filter out 1/f noise. A phase selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference of output same as that of input. The cascaded hybrid PLL fabricated in 65nm CMOS process burns 17mW and occupies 0.4mm(2). The measured jitters are 1.1ns(pp) and 223.6ps(rms), respectively with a multiplication factor of 1,024. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/CICC.2009.5280849 | PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE |
Keywords | Field | DocType |
cmos integrated circuits,piecewise linear,phase locked loops,pixel,synchronization,calibration,jitter,time to digital converter | Phase-locked loop,Synchronization,Control theory,Computer science,CMOS,Electronic engineering,Control engineering,Multiplication,Jitter,Piecewise linear function,Time-to-digital converter,Clock rate | Conference |
Citations | PageRank | References |
5 | 0.90 | 6 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Minyoung Song | 1 | 40 | 6.89 |
| Young-Ho Kwak | 2 | 44 | 6.75 |
| Sung-Hoon Ahn | 3 | 65 | 15.09 |
| Wooseok Kim | 4 | 29 | 5.64 |
| Byeong-Ha Park | 5 | 63 | 12.13 |
| Chulwoo Kim | 6 | 397 | 74.58 |