Young-Ho Kwak - Citegraph

Author Info

Name	Affiliation	Papers
YOUNG-HO KWAK	Korea Univ, Dept Elect & Comp Engn, Anam Dong 136713, South Korea	13
Collaborators	Citations	PageRank
20	44	6.75
Referers	Referees	References
152	191	61

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100191

Publications (13 rows)

Collaborators (20 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process	4	0.45	2013
10–315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation	0	0.34	2013
A 1.62 Gb/s–2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection	12	0.80	2013
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile.	6	0.50	2012
250 Mbps-5 Gbps Wide-Range Cdr With Digital Vernier Phase Shifting And Dual-Mode Control In 0.13 Mu M Cmos	0	0.34	2011
A 0.076mm2 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS.	0	0.34	2011
A Gb/S Plus Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time	0	0.34	2010
A Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time	2	0.42	2010
A Gb/s+ slew-rate/impedance-controlled output driver with single-cycle compensation time	0	0.34	2010
A 10mhz To 315mhz Cascaded Hybrid Pll With Piecewise Linear Calibrated Tdc	5	0.90	2009
A slew-rate controlled output driver with one-cycle tuning time	0	0.34	2008
A One-Cycle Lock Time Slew-Rate-Controlled Output Driver.	13	1.24	2007
Differential Pass Transistor Pulsed Latch.	2	0.41	2005

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