Name
Abstract | ||
|---|---|---|
In this paper the underlying design method for massively parallel processor arrays allows to exploit parallelism in a broader range because of not considering the I/O-variables during the design process of a full size array. As a consequence of this approach a reallocation of the I/O-ports of the I/O-variables at the boundary processors of the processor array is necessary. Algorithms will be described for the reallocation of the I/O-ports at the array boundaries leading to a minimal additional latency and taking systolic constraints into account. Integer linear programming is used to solve the arising optimization problems. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/EMPDP.1996.500625 | PDP |
Keywords | Field | DocType |
minimal additional latency,array boundary,parallel processor arrays,integer linear programming,design process,processor array,underlying design method,boundary processor,parallel processor array,full size array,broader range,design method,space technology,algorithm design and analysis,linear programming,concurrent computing,integer programming,embedded computing,design methodology,optimization problems,process design | Massively parallel,Processor array,Computer science,Branch and price,Parallel computing,Input/output,Integer programming,Engineering design process,Linear programming,Optimization problem | Conference |
Citations | PageRank | References |
2 | 0.46 | 4 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dirk Fimmel | 1 | 48 | 6.45 |
| Renate Merker | 2 | 159 | 20.59 |