Name
Title | ||
|---|---|---|
MPEG Macroblock Parsing and Pel Reconstruction on an FPGA-Augmented TriMedia Processor |
Abstract | ||
|---|---|---|
Abstract: A new asynchronous pipeline design is introduced for high-speed applications. The pipeline uses simple transparent latches in its datapath, and small latch controllers consisting of only a single gate per pipeline stage. This simple stage structure ... |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/ICCD.2001.955061 | ICCD |
Keywords | Field | DocType |
single gate,fpga-augmented trimedia processor,high-speed application,pipeline stage,simple stage structure,pel reconstruction,mpeg macroblock parsing,new asynchronous pipeline design,quantization,computer architecture,data compression,fpga,grammars,hardware,variable length code,vliw,computer applications,field programmable gate arrays,decoding,latency | Macroblock,Computer architecture,Computer science,Very long instruction word,Parallel computing,Field-programmable gate array,Real-time computing,Decoding methods,Parsing,Quantization (signal processing),Data compression,TriMedia | Conference |
ISSN | Citations | PageRank |
1063-6404 | 9 | 1.11 |
References | Authors | |
11 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mihai Sima | 1 | 95 | 16.66 |
| Sorin Cotofana | 2 | 245 | 39.03 |
| s vasseliadis | 3 | 9 | 1.11 |
| Jos T. J. van Eijndhoven | 4 | 135 | 16.27 |
| Kees A. Vissers | 5 | 1136 | 104.30 |