Name
Abstract | ||
|---|---|---|
The paper presents a preemptive test application scheme for system-on-chip (SoC) designs with EDT-based compression. It seamlessly combines a new test data reduction technique with a test scheduling algorithm and a novel test access mechanism. It is particularly well suited for SoC devices comprising non-isolated cores, i.e., blocks that occasionally need to be tested simultaneously. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TEST.2010.5699227 | INTERNATIONAL TEST CONFERENCE 2010 |
Keywords | Field | DocType |
encoding,system on a chip,system on chip,merging,multicore processing,dynamic channel allocation,job shop scheduling,testing,data compression | Compression (physics),Job shop scheduling,System on a chip,Computer science,Real-time computing,Test data,Data compression,Multi-core processor,Channel allocation schemes,Encoding (memory),Embedded system | Conference |
ISSN | Citations | PageRank |
1089-3539 | 7 | 0.51 |
References | Authors | |
36 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mark Kassab | 1 | 654 | 48.74 |
| Grzegorz Mrugalski | 2 | 501 | 35.90 |
| Nilanjan Mukherjee | 3 | 801 | 57.26 |
| Janusz Rajski | 4 | 2460 | 201.28 |
| Jakub Janicki | 5 | 46 | 4.31 |
| Jerzy Tyszer | 6 | 838 | 74.98 |