Name
Abstract | ||
|---|---|---|
In this paper, we present a pipelined Network of PLA based circuit design approach. Our approach can be used to realize an arbitrary logic circuit with an extremely high throughput and low latency. Using logic synthesis tools to decompose a logic circuit into this framework, and appropriately inserting "stutter" blocks to balance the logical depth of all paths in the decomposed circuit, we come up with a pipelined network of PLA netlist. We have demonstrated the effectiveness of the approach via SPICE simulations and layout generation experiments. Throughput, latency, and area are compared with competing approaches, demonstrating the power of this design style. We show that our approach has a 75% better throughput than the asynchronous micropipelining based technique, and a latency which is 63% that of the asynchronous scheme. Both techniques were implemented in a super-threshold fashion. We have also conducted Monte Carlo experiments to validate the approach under variations. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1366110.1366162 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
pipelined network,low latency,arbitrary logic circuit,better throughput,logic synthesis tool,pla netlist,circuit design approach,asynchronous scheme,logic circuit,decomposed circuit,high throughput,circuit design,pipelining,logic synthesis,synchronous | Logic synthesis,Netlist,Logic gate,Computer science,Logic optimization,Parallel computing,Circuit extraction,Circuit design,Real-time computing,Electronic engineering,Register-transfer level,Asynchronous circuit | Conference |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Suganth Paul | 1 | 35 | 2.57 |
| Rajesh Garg | 2 | 76 | 8.45 |
| Sunil P. Khatri | 3 | 1213 | 137.09 |