Rajesh Garg - Citegraph

Author Info

Name	Affiliation	Papers
RAJESH GARG	Dept . of Electrical and Computer Engineering\|Texas A&M University	10
Collaborators	Citations	PageRank
12	76	8.45
Referers	Referees	References
187	161	73

Search Limit

100187

Publications (10 rows)

Collaborators (12 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Efficient analytical determination of the SEU-induced pulse shape	6	0.56	2009
Circuit-level design approaches for radiation-hard digital electronics	9	1.51	2009
A PLL Design based on a Standing Wave Resonant Oscillator	5	0.97	2009
Design and implementation of a sub-threshold BFSK transmitter	2	0.40	2009
SEU hardened clock regeneration circuits	4	0.63	2009
A fast, analytical estimator for the SEU-induced pulse width in combinational designs	16	0.95	2008
Pipelined network of PLA based circuit design	0	0.34	2008
A single-supply true voltage level shifter	1	0.42	2008
A methodology for interconnect dimension determination	0	0.34	2007
A design approach for radiation-hard digital electronics	33	2.33	2006

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