Paper Info
Title
Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits
Abstract
In this paper, we analyze combinational logic circuits using "fan-out constraints" to generate tests for single stuck-at faults. A method of circuit transformation is employed to explicitly derive "fan-out constraints for controllability" and "fan-out constraints for observability," which are dependent Boolean functions and Boolen difference functions, respectively, in terms of primary inputs and fan-out stems. Then, a simplified version of a test generation algorithm which uses only the fan-out constraints for controllability at internal reconvergent fan-out stems is illustrated with an example. This approach differs from earlier work in that information about the circuit is accumulated and refined as the test generation process proceeds. In this test generation algorithm, the dependencies among fan-out nodes are ordered and solved in a hierarchical fashion so that the computation time for generating tests and detecting redundant faults can be greatly reduced--especially for locally redundant or "difficult" faults.
Year
DOI
Venue
1986
10.1109/TCAD.1986.1270227
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Keywords
DocType
Volume
redundant fault,redundant fault detection,test generation process proceed,fan-out constraints,fan-out constraints for controllability,internal reconvergent fan-out,boolen difference function,reconvergent fan-out,Boolean difference,computation time,generate tests,fan-out node,stuck faults,test generation algorithm,circuit transformation,combinational logic circuit,Combinational logic,fan-out constraint,fan-out constraints for observability,combinational logic circuits
Journal
5
Issue
Citations 
PageRank 
4
2
0.86
References 
Authors
5
2
Name
Order
Citations
PageRank
Ki Soo Hwang1138.55
M. R. Mercer235347.36