Paper Info
Title
Scheduling-based test-case generation for verification of multimedia SoCs
Abstract
Multimedia SoCs are characterized by a main controller that directs the activity of several cores, each of which is in charge of a stage in the processing of a media stream. The verification of these SoCs is a significant challenge due to time-to-market constraints and system complexity. We present a novel approach to system-level, random test case generation for multimedia SoCs, and a tool, called SoCVer, that implements this approach. We use the SoC's main controller point of view for controlling the flow of data in the SoC. Test case generation is done by allocating processing tasks to the various cores and determining which core processes which data item at what time. Solving these scheduling problems allows SoCVer to generate software for the SoC's main controller; this software coordinates and synchronizes the operations of all the cores on the chip without the need for the real operational software. We demonstrate the use of SoCVer using a DVD player SoC.
Year
DOI
Venue
2006
10.1145/1146909.1146999
DAC
Keywords
Field
DocType
test case generation,processing task,main controller,novel approach,data item,random test case generation,multimedia socs,main controller point,real operational software,dvd player,scheduling-based test-case generation,network synthesis,scheduling problem,system on a chip,chip,functional verification,random testing,automatic test pattern generation,verification,digital circuits,system on chip
Functional verification,Digital electronics,Computer science,Scheduling (computing),DVD player,Electronic engineering,Real-time computing,Software,Automatic test pattern generation,Control theory,System on a chip,Multimedia,Embedded system
Conference
ISBN
Citations 
PageRank 
1-59593-381-6
5
0.64
References 
Authors
4
5
Name
Order
Citations
PageRank
Amir Nahir117214.84
Avi Ziv246572.49
roy emek313613.59
Tal Keidar450.64
Nir Ronen550.64