Automatic Scalable System for the Coverage-Directed Generation (CDG) Problem | 0 | 0.34 | 2021 |
Using Deep Neural Networks And Derivative Free Optimization To Accelerate Coverage Closure | 0 | 0.34 | 2021 |
Late Breaking Results: Friends - Finding Related Interesting Events Via Neighbor Detection | 0 | 0.34 | 2020 |
Using DNNs and Smart Sampling for Coverage Closure Acceleration | 1 | 0.39 | 2020 |
ML for CAD - Where is the Treasure Hiding? | 0 | 0.34 | 2020 |
Using Machine Learning Clustering To Find Large Coverage Holes | 0 | 0.34 | 2020 |
Challenges and Solutions in Post-Silicon Validation of High-end Processors (Invited Tutorial) | 0 | 0.34 | 2019 |
Solving Constraint Satisfaction Problems Containing Vectors Of Unknown Size | 1 | 0.37 | 2017 |
Cost-effective analysis of post-silicon functional coverage events. | 3 | 0.40 | 2017 |
Post-Silicon Validation in the SoC Era: A Tutorial Introduction. | 9 | 0.67 | 2017 |
Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification. | 1 | 0.36 | 2016 |
The Verification Cockpit - Creating the Dream Playground for Data Analytics over the Verification Process. | 2 | 0.43 | 2015 |
Verification of Transactional Memory in POWER8 | 9 | 0.44 | 2014 |
Enhancing Scenario Quality Using Quasi-Events. | 0 | 0.34 | 2014 |
Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms | 1 | 0.36 | 2013 |
Approximating checkers for simulation acceleration | 3 | 0.40 | 2012 |
Generating instruction streams using abstract CSP | 5 | 0.47 | 2012 |
A novel approach for implementing microarchitectural verification plans in processor designs | 1 | 0.38 | 2012 |
Concurrent Generation of Concurrent Programs for Post-Silicon Validation | 5 | 0.42 | 2012 |
Checking architectural outputs instruction-by-instruction on acceleration platforms | 4 | 0.45 | 2012 |
Automatic boosting of cross-product coverage using Bayesian networks | 1 | 0.43 | 2011 |
Threadmill: A post-silicon exerciser for multi-threaded processors | 21 | 0.75 | 2011 |
Reverse coverage analysis | 1 | 0.37 | 2011 |
Learning microarchitectural behaviors to improve stimuli generation quality | 14 | 0.90 | 2011 |
A probabilistic analysis of coverage methods | 1 | 0.36 | 2011 |
Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor | 11 | 0.67 | 2011 |
Bridging pre-silicon verification and post-silicon validation | 16 | 0.92 | 2010 |
Reaching coverage closure in post-silicon validation | 20 | 0.91 | 2010 |
Using Bayesian networks and virtual coverage to hit hard-to-reach events | 2 | 0.51 | 2009 |
Ensuring Functional Closure of a Multi-core SoC through Verification Planning, Implementation and Execution | 0 | 0.34 | 2008 |
Automatic Boosting of Cross-Product Coverage Using Bayesian Networks | 5 | 0.55 | 2008 |
A probabilistic alternative to regression suites | 3 | 0.46 | 2008 |
Hardware and Software, Verification and Testing, Second International Haifa Verification Conference, HVC 2006, Haifa, Israel, October 23-26, 2006. Revised Selected Papers | 14 | 1.60 | 2007 |
Verification coverage: when is enough enough | 0 | 0.34 | 2007 |
Using virtual coverage to hit hard-to-reach events | 3 | 0.44 | 2007 |
Scheduling-based test-case generation for verification of multimedia SoCs | 5 | 0.64 | 2006 |
Using linear programming techniques for scheduling-based random test-case generation | 1 | 0.37 | 2006 |
Panel: Functional coverage - is your design exposed? | 0 | 0.34 | 2005 |
Defining coverage views to improve functional coverage analysis | 8 | 0.66 | 2004 |
Probabilistic regression suites for functional verification | 5 | 0.54 | 2004 |
Probabilistic Alternative Regression Suites | 0 | 0.34 | 2004 |
Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification | 78 | 4.18 | 2004 |
Coverage directed test generation for functional verification using bayesian networks | 92 | 4.90 | 2003 |
Panel: What's the next 'big thing' in simulation-based verification? | 0 | 0.34 | 2003 |
Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions | 11 | 0.93 | 2003 |
Hole analysis for functional coverage data | 26 | 1.89 | 2002 |
Analysis of Checkpointing Schemes with Task Duplication | 15 | 0.87 | 1998 |
User defined coverage—a tool supported methodology for design verification | 59 | 37.05 | 1998 |
Design reliability—estimation through statistical analysis of bug discovery data | 6 | 1.39 | 1998 |
Placement and routing for a field programmable multi-chip module | 2 | 0.59 | 1994 |