Paper Info
Title
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Abstract
Negative Bias Temperature Instability (NBTI), a PMOS aging phenomenon causing significant loss on circuit performance and lifetime, has become a critical challenge for temporal reliability concerns in nanoscale designs. Aggressive technology scaling trends, such as thinner gate oxide without proportional downscaling of supply voltage, necessitate a design optimization flow considering NBTI effects at the early stages. In this paper, we present a novel framework using joint logic restructuring and pin reordering to mitigate NBTI-induced performance degradation. Based on detecting functional symmetries and transistor stacking effects, the proposed methodology involves only wire perturbation and introduces no gate area overhead at all. Experimental results reveal that, by using this approach, on average 56% of performance loss due to NBTI can be recovered. Moreover, our methodology reduces the number of critical transistors remaining under severe NBTI and thus, transistor resizing can be applied to further mitigate NBTI effects with low area overhead.
Year
DOI
Venue
2009
10.1109/DATE.2009.5090636
DATE
Keywords
Field
DocType
gate area overhead,critical transistor,critical challenge,performance loss,proposed methodology,circuit performance,nbti-induced performance degradation,nbti effect,low area overhead,joint logic restructuring,severe nbti,degradation,logic,design optimization,placement,topology,transistors,stacking,aging,logic gates,mathematical model,voltage,negative bias temperature instability,ageing
Logic gate,Computer science,Circuit reliability,Voltage,Electronic engineering,Negative-bias temperature instability,Gate oxide,PMOS logic,Transistor,MOSFET
Conference
ISSN
Citations 
PageRank 
1530-1591
28
1.07
References 
Authors
12
2
Name
Order
Citations
PageRank
Kai-Chiang Wu111313.98
Diana Marculescu22725223.87