Name
Abstract | ||
|---|---|---|
A scalable 64-lane chip-to-chip I/O, with per-lane data rate of 2-16 Gb/s is demonstrated in 32-nm low-power CMOS technology. At maximum aggregate bandwidth of 1.024 Tb/s across 50-cm channel length, the link consumes 2.7 W from a 1.08-V supply, corresponding to 2.6 pJ/bit. As bandwidth demand decreases, scaling the per-lane data rate to 4 Gb/s and power supply to 0.65 V provides 1/4 of the maximu... |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/JSSC.2013.2279052 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Clocks,Bandwidth,Transmitters,CMOS integrated circuits,Receivers,Voltage-controlled oscillators,Connectors | Electrical efficiency,Transmitter,Computer science,Communication channel,Electronic engineering,Error detection and correction,CMOS,Bandwidth (signal processing),Parallel I/O,Low-power electronics | Journal |
Volume | Issue | ISSN |
48 | 12 | 0018-9200 |
Citations | PageRank | References |
12 | 0.86 | 9 |
Authors | ||
10 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mozhgan Mansuri | 1 | 154 | 25.15 |
| James E. Jaussi | 2 | 125 | 26.64 |
| Joseph T. Kennedy | 3 | 106 | 17.78 |
| Tzu-Chien Hsueh | 4 | 36 | 5.63 |
| Shashi Shekhar | 5 | 4352 | 1098.43 |
| Ganesh Balamurugan | 6 | 144 | 20.77 |
| Frank O'Mahony | 7 | 102 | 20.28 |
| Clark Roberts | 8 | 63 | 7.25 |
| Randy Mooney | 9 | 90 | 17.88 |
| Bryan Casper | 10 | 147 | 25.64 |