| Silicon Photonic Micro-Ring Modulator-based 4 x 112 Gb/s O-band WDM Transmitter with Ring Photocurrent-based Thermal Control in 28nm CMOS | 0 | 0.34 | 2021 |
| A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control | 2 | 0.44 | 2021 |
| A 4×50 Gb/s All-Silicon Ring-based WDM Transceiver with CMOS IC. | 0 | 0.34 | 2021 |
| 11.6 A 100Gb/s-8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOS | 1 | 0.41 | 2021 |
| 12.1 A 3D-Integrated Microring-Based 112Gb/s PAM-4 Silicon-Photonic Transmitter with Integrated Nonlinear Equalization and Thermal Control | 0 | 0.34 | 2020 |
| 56g/112g Link Foundations Standards, Link Budgets & Models | 0 | 0.34 | 2019 |
| A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS. | 0 | 0.34 | 2018 |
| A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS | 1 | 0.39 | 2015 |
| 26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS | 5 | 0.88 | 2014 |
| A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS | 13 | 1.21 | 2013 |
| A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS. | 12 | 0.86 | 2013 |
| A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS. | 24 | 2.92 | 2010 |
| A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS. | 4 | 0.47 | 2010 |
| A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS | 2 | 0.81 | 2010 |
| Strong Injection Locking in Low- $Q$ LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver | 16 | 1.34 | 2009 |
| Strong injection locking in low-Q LC oscillators: modeling and application in a forwarded-clock I/O receiver | 0 | 0.34 | 2009 |
| Strong injection locking of low-Q LC oscillators | 4 | 0.79 | 2008 |
| Joint equalization and coding for on-chip bus communication | 8 | 0.56 | 2008 |
| Future Microprocessor Interfaces: Analysis, Design And Optimization | 11 | 1.27 | 2007 |
| Joint Equalization and Coding for On-Chip Bus Communication | 6 | 0.84 | 2005 |
| Modeling and mitigation of jitter in multiGbps source-synchronous I/O links | 10 | 2.07 | 2003 |
| The twin-transistor noise-tolerant dynamic circuit technique | 25 | 3.48 | 2001 |
