Title
Design of new optimized architecture processor for DWT
Abstract
This paper presents a VLSI implementation of One Dimensional Direct Discrete Wavelet transform (1-D DWT). The DDWT can be viewed as a multi-resolution decomposition of a signal. This means that it decomposes a signal into its components in different frequency bands (octave bands). We propose a new architecture using parallel filters. We consider the implementation of 1-D three levels DWT. The proposed architecture is simple and offers 16-bit precision on input and output data. It is constituted of three basic units: one register bank, four filters, and a control unit. The filters are of different lengths and with new coefficients derived from Daubechies filter coefficients. The designed processor architecture requires no interface circuitry for interconnection to a standard communication bus. The architecture can compute DWT at a data rate of 12×10 6 samples/s corresponding to a typical clock speed of 12 MHz. The architecture is simulated at the gate level in VLSI.
Year
DOI
Venue
2000
10.1006/rtim.1999.0178
Real-Time Imaging
Keywords
Field
DocType
new optimized architecture processor,processor architecture,discrete wavelet transform
Computer science,Parallel computing,Input/output,Real-time computing,Control unit,Discrete wavelet transform,Systems architecture,Computer hardware,Very-large-scale integration,Clock rate,Filter design,Microarchitecture
Journal
Volume
Issue
ISSN
6
4
Real-Time Imaging
Citations 
PageRank 
References 
3
0.42
16
Authors
5
Name
Order
Citations
PageRank
Chokri Souani1418.75
Mohamed Atri215427.75
Mohamed Abid3243.76
Kholdoun Torki4606.70
Rached Tourki514425.21