Chokri Souani - Citegraph

Author Info

Name	Affiliation	Papers
CHOKRI SOUANI	Laboratory of Microelectronics and Instrumentation µEI, Faculty of Sciences of Monastir, Boulevard de l'environnement, 5019 Monastir, Tunisia	22
Collaborators	Citations	PageRank
44	41	8.75
Referers	Referees	References
100	421	177

Search Limit

100421

Publications (22 rows)

Collaborators (44 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Face recognition in unconstrained environment with CNN	2	0.36	2021
Full Python Interface Control: Auto Generation And Adaptation of Deep Neural Networks For Edge Computing and IoT Applications FPGA-Based Acceleration	0	0.34	2021
A Novel Automate Python Edge-To-Edge: From Automated Generation On Cloud To User Application Deployment On Edge Of Deep Neural Networks For Low Power Iot Systems Fpga-Based Acceleration	0	0.34	2021
Low Cost and Low Power Stacked Sparse Autoencoder Hardware Acceleration for Deep Learning Edge Computing Applications	0	0.34	2020
An Efficient Parallel Implementation of Face Detection System Using CUDA	0	0.34	2020
Embedded Real-Time System for Traffic Sign Recognition on ARM Processor	0	0.34	2020
Real-time embedded system for traffic sign recognition based on ZedBoard	2	0.35	2019
Design of efficient embedded system for road sign recognition.	0	0.34	2019
The estimation of buried empty cylindrical tubes characteristics using GPR	0	0.34	2018
Novel Technique For 3d Face Recognition Using Anthropometric Methodology	3	0.42	2018
FFT implementation and optimization on FPGA	0	0.34	2018
Towards Its Vision Assisted Cooperative Perception	0	0.34	2018
Mapping Of Sewer Lines Using Gpr: A Case Study In Tunisia	0	0.34	2018
Architectural exploration of multilayer perceptron models for on-chip and real-time road sign classification.	0	0.34	2018
Novel Technique for 3D Face Segmentation and Landmarking	0	0.34	2016
Real-time hardware/software co-design of a traffic sign recognition system using Zynq FPGA	0	0.34	2016
Embedded system for road sign detection using MicroBlaze	4	0.46	2015
Efficient algorithm for automatic road sign recognition and its hardware implementation	15	0.75	2014
Design and implementation of optimized architecture for computing the 2D-DWT for JPEG2000 compression	2	0.44	2010
DSP Implementation and Performances Evaluation of JPEG2000 Wavelet Filters	0	0.34	2008
VLSI design of 1-D DWT architecture with parallel filters	10	0.81	2000
Design of new optimized architecture processor for DWT	3	0.42	2000