Name
Title | ||
|---|---|---|
A 2.5 - 10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization |
Abstract | ||
|---|---|---|
This paper describes a technique for stabilizing the binary phase detector (PD) gain under various jitter conditions. A dead zone in the phase detector estimates the magnitude of high-frequency data jitter, and the resulting jitter information is used to control the charge-pump current. An alternating edge-sampling (AES) PD reduces hardware overhead by removing possible redundancies in previous de... |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/JSSC.2003.818290 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Transceivers,Phase detection,Jitter,Detectors,Clocks,Phase estimation,Charge pumps,Hardware,Sampling methods,Voltage-controlled oscillators | Journal | 38 |
Issue | ISSN | Citations |
11 | 0018-9200 | 19 |
PageRank | References | Authors |
3.60 | 6 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| B.-J. Lee | 1 | 104 | 19.31 |
| Moon-Sang Hwang | 2 | 83 | 16.23 |
| Sang-Hyun Lee | 3 | 45 | 10.09 |
| Deog-Kyoon Jeong | 4 | 626 | 119.05 |