Name
Abstract | ||
|---|---|---|
This paper presents an analysis of transaction of multiprocessor platform with bus matrix. Simple equations about the latency and throughput for this architecture are derived. From this equation we evaluate operating frequency to meet latency and throughput requirements. This architecture is modeled as transaction level model (TLM) in SystemC in order to confirm the validation of the governing equation. The result of simulation corresponds to that of the derived equation. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/IWSOC.2005.108 | IWSOC |
Keywords | Field | DocType |
bus matrix,throughput requirement,transaction level model,simple equation,simulation corresponds,multiprocessor platform,transaction analysis,throughput,testing,frequency,information analysis,system on chip | System on a chip,Computer science,Matrix (mathematics),Latency (engineering),Parallel computing,SystemC,Multiprocessing,Throughput,Time to market,Database transaction,Embedded system | Conference |
ISBN | Citations | PageRank |
0-7695-2403-6 | 0 | 0.34 |
References | Authors | |
3 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seungbeom Lee | 1 | 45 | 7.04 |
| Sin-Chong Park | 2 | 80 | 22.58 |