Name
Abstract | ||
|---|---|---|
In this paper we introduce a statistical quality model for delay testing that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that predicts the chip defect level that cause delay failure, including marginal small delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1093/ietele/e89-c.3.349 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
delay testing, quality model, defect distribution | Industrial design,Fault coverage,Electronic engineering,Chip,Parametric statistics,Statistical model,Process variation,Engineering,Elmore delay,Fault model | Journal |
Volume | Issue | ISSN |
E89C | 3 | 1745-1353 |
Citations | PageRank | References |
1 | 0.36 | 10 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yasuo Sato | 1 | 38 | 4.46 |
| Shuji Hamada | 2 | 123 | 7.13 |
| Toshiyuki Maeda | 3 | 213 | 25.86 |
| Atsuo Takatori | 4 | 5 | 0.81 |
| Seiji Kajihara | 5 | 989 | 73.60 |