Yasuo Sato - Citegraph

Author Info

Name	Affiliation	Papers
YASUO SATO	Semicond Technol Acad Res Ctr, Yokohama, Kanagawa, Japan	10
Collaborators	Citations	PageRank
22	38	4.46
Referers	Referees	References
106	205	126

Search Limit

100205

Publications (10 rows)

Collaborators (22 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
On-Chip Delay Measurement for In-Field Test of FPGAs	0	0.34	2019
Genetic algorithm based approach for segmented testing	2	0.38	2011
On Delay Test Quality for Test Cubes.	0	0.34	2010
Post-BIST Fault Diagnosis for Multiple Faults	0	0.34	2008
Effective Post-BIST Fault Diagnosis for Multiple Faults	1	0.39	2006
A dynamic test compaction procedure for high-quality path delay testing	3	0.42	2006
A Framework Of High-Quality Transition Fault Atpg For Scan Circuits	19	0.89	2006
A Statistical Quality Model For Delay Testing	1	0.36	2006
Recognition Of Sensitized Longest Paths In Transition Delay Test	4	0.45	2006
Path delay test compaction with process variation tolerance	8	0.56	2005

1