Name
Abstract | ||
|---|---|---|
Voltage scaling is one of the most effective mechanisms to improve microprocessors' energy efficiency. However, processors cannot operate reliably below a minimum voltage, Vccmin, since hardware structures may fail. Cell failures in large memory arrays (e.g., caches) typically determine Vccmin for the whole processor. We observe that most cache lines exhibit zero or one failures at low voltages. However, a few lines, especially in large caches, exhibit multi-bit failures and increase Vccmin. Previous solutions either significantly reduce cache capacity to enable uniform error correction across all lines, or significantly increase latency and bandwidth overheads when amortizing the cost of error-correcting codes (ECC) over large lines. In this paper, we propose a novel cache architecture that uses variable-strength error-correcting codes (VS-ECC). In the common case, lines with zero or one failures use a simple and fast ECC. A small number of lines with multi-bit failures use a strong multi-bit ECC that requires some additional area and latency. We present a novel dynamic cache characterization mechanism to determine which lines will exhibit multi-bit failures. In particular, we use multi-bit correction to protect a fraction of the cache after switching to low voltage, while dynamically testing the remaining lines for multi-bit failures. Compared to prior multi-bit-correcting proposals, VS-ECC significantly reduces power and energy, avoids significant reductions in cache capacity, incurs little area overhead, and avoids large increases in latency and bandwidth. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/2000064.2000118 | ISCA |
Keywords | Field | DocType |
multi-bit correction,novel cache architecture,variable-strength error-correcting code,energy-efficient cache design,exhibit multi-bit failure,strong multi-bit ecc,novel dynamic cache characterization,large cache,cache capacity,low voltage,cache lines exhibit zero,multi-bit failure,reliability,error correction code,bandwidth,testing,energy efficient,energy efficiency,error correction | Cache pollution,Latency (engineering),Computer science,Cache,Parallel computing,Cache-only memory architecture,Error detection and correction,Cache algorithms,Real-time computing,Cache coloring,Low voltage | Conference |
Volume | Issue | ISSN |
39 | 3 | 0163-5964 |
Citations | PageRank | References |
71 | 2.07 | 15 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alaa R. Alameldeen | 1 | 1672 | 80.06 |
| Ilya Wagner | 2 | 204 | 10.01 |
| Zeshan Chishti | 3 | 723 | 34.65 |
| Wu Wei | 4 | 204 | 14.84 |
| Chris Wilkerson | 5 | 1575 | 61.73 |
| Shih-Lien Lu | 6 | 958 | 67.34 |