| Improving Streaming Graph Processing Performance using Input Knowledge | 4 | 0.36 | 2021 |
| SAGA-Bench: Software and Hardware Characterization of Streaming Graph Analytics Workloads | 1 | 0.34 | 2020 |
| TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory Systems | 0 | 0.34 | 2019 |
| ZCOMP: Reducing DNN Cross-Layer Memory Footprint Using Vector Extensions | 5 | 0.44 | 2019 |
| Memory system characterization of deep learning workloads | 2 | 0.36 | 2019 |
| Reducing DRAM Refresh Overheads with Refresh-Access Parallelism. | 0 | 0.34 | 2018 |
| Flexible associativity for DRAM caches | 0 | 0.34 | 2018 |
| Hardware-Software Co-design to Mitigate DRAM Refresh Overheads: A Case for Refresh-Aware Process Scheduling. | 11 | 0.49 | 2017 |
| DRAM Refresh Mechanisms, Penalties, and Trade-Offs | 17 | 0.79 | 2016 |
| The Case for Associative DRAM Caches. | 0 | 0.34 | 2016 |
| Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses. | 0 | 0.34 | 2016 |
| Path confidence based lookahead prefetching. | 10 | 0.46 | 2016 |
| Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions | 17 | 0.62 | 2015 |
| Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance | 0 | 0.34 | 2015 |
| Efficiently prefetching complex address patterns | 27 | 0.86 | 2015 |
| Improving DRAM performance by parallelizing refreshes with accesses | 40 | 1.02 | 2014 |
| Transparent Hardware Management of Stacked DRAM as Part of Memory | 40 | 1.12 | 2014 |
| Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers | 30 | 0.85 | 2014 |
| Coordinated refresh: energy efficient techniques for DRAM refresh scheduling | 14 | 0.55 | 2013 |
| Operating SECDED-based caches at ultra-low voltage with FLAIR | 13 | 0.52 | 2013 |
| Adaptive Cache Design to Enable Reliable Low-Voltage Operation | 20 | 0.83 | 2011 |
| Energy-efficient cache design using variable-strength error-correcting codes | 71 | 2.07 | 2011 |
| Improving cache lifetime reliability at ultra-low voltages | 90 | 2.77 | 2009 |
| Trading Off Cache Capacity for Low-Voltage Operation | 5 | 0.44 | 2009 |
| Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies | 2 | 0.38 | 2008 |
| Shapeshifter: Dynamically changing pipeline width and speed to address process variations | 18 | 0.74 | 2008 |
| Optimizing Replication, Communication, and Capacity Allocation in CMPs | 165 | 9.72 | 2005 |
| Wire Delay is Not a Problem for SMT (In the Near Future) | 14 | 0.75 | 2004 |
| Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures | 107 | 6.13 | 2003 |
