Name
Abstract | ||
|---|---|---|
The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size that is fixed at design time. Miss rates for different applications can be improved if the line size could be adjusted dynamically at run time.We propose a system where the compiler can set the cache line size for different portions of the program and we show that the miss rate is greatly reduced as a result of this dynamic resizing. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1007/3-540-44570-6_15 | Intelligent Memory Systems |
Keywords | Field | DocType |
cache memory system,compiler-directed cache line size,computer system,cache line size,different application,dynamic resizing,traditional cache memory system,design time,different portion,line size,run time,cache memory | Cache-oblivious algorithm,Cache invalidation,Cache pollution,Cache,Computer science,Parallel computing,Cache algorithms,Page cache,Cache coloring,Smart Cache | Conference |
ISBN | Citations | PageRank |
3-540-42328-1 | 6 | 0.65 |
References | Authors | |
5 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dan Nicolaescu | 1 | 57 | 4.70 |
| Xiaomei Ji | 2 | 75 | 5.95 |
| Alexander V. Veidenbaum | 3 | 757 | 78.24 |
| Alexandru Nicolau | 4 | 2265 | 307.74 |
| Rajesh K. Gupta | 5 | 4570 | 390.84 |