| Hyperdimensional hashing: a robust and efficient dynamic hash table | 0 | 0.34 | 2022 |
| GraphHD: Efficient graph classification using hyperdimensional computing | 0 | 0.34 | 2022 |
| Class-Modeling of Septic Shock With Hyperdimensional Computing | 0 | 0.34 | 2021 |
| NumbaSummarizer: A Python Library for Simplified Vectorization Reports | 0 | 0.34 | 2020 |
| MCompiler: A Synergistic Compilation Framework. | 0 | 0.34 | 2019 |
| Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines | 0 | 0.34 | 2018 |
| LORE: A loop repository for the evaluation of compilers | 1 | 0.36 | 2017 |
| Using Hardware Counters to Predict Vectorization. | 0 | 0.34 | 2017 |
| Nsf Expedition On Variability-Aware Software: Recent Results And Contributions | 3 | 0.37 | 2015 |
| Software fault tolerance for FPUs via vectorization | 4 | 0.40 | 2015 |
| Fault Tolerant Scheduling for Parallel Loops on Shared Memory Systems. | 0 | 0.34 | 2015 |
| WebRTCbench: a benchmark for performance assessment of webRTC implementations | 2 | 0.56 | 2015 |
| On-chip self-awareness using cyberphysical-systems-on-chip (CPSoC) | 9 | 0.56 | 2014 |
| On the determination of inlining vectors for program optimization | 3 | 0.41 | 2013 |
| A fault tolerant self-scheduling scheme for parallel loops on shared memory systems | 4 | 0.42 | 2012 |
| Just in Time Load Balancing. | 2 | 0.38 | 2012 |
| Exploiting parallelism in matrix-computation kernels for symmetric multiprocessor systems: Matrix-multiplication and matrix-addition algorithm optimizations by software pipelining and threads allocation | 12 | 0.72 | 2011 |
| Improving the Accuracy of High Performance BLAS Implementations Using Adaptive Blocked Algorithms | 1 | 0.37 | 2011 |
| Improving accuracy for matrix multiplications on GPUs | 2 | 0.64 | 2011 |
| Exploitation of nested thread-level speculative parallelism on multi-core systems | 3 | 0.39 | 2010 |
| Synchronization optimizations for efficient execution on multi-cores | 9 | 0.58 | 2009 |
| Efficient Scheduling of Nested Parallel Loops on Multi-Core Systems | 6 | 0.56 | 2009 |
| Adaptive Winograd's matrix multiplications | 12 | 0.86 | 2009 |
| Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009 | 68 | 7.12 | 2009 |
| Cache-aware iteration space partitioning | 3 | 0.44 | 2008 |
| Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium® architecture | 1 | 0.48 | 2007 |
| A simplified java bytecode compilation system for resource-constrained embedded processors | 5 | 0.46 | 2007 |
| Adaptive Strassen's matrix multiplication | 7 | 0.64 | 2007 |
| Annotation Integration and Trade-off Analysis for Multimedia Applications | 0 | 0.34 | 2007 |
| Challenges in exploitation of loop parallelism in embedded applications | 9 | 0.51 | 2006 |
| On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings | 22 | 0.96 | 2006 |
| Energy efficient watermarking on mobile devices using proxy-based partitioning | 5 | 0.51 | 2006 |
| An efficient approach for self-scheduling parallel loops on multiprogrammed parallel computers | 2 | 0.39 | 2005 |
| An Efficient Load Balancing Scheme for Grid-based High Performance Scientific Computing | 8 | 0.48 | 2005 |
| Using recursion to boost ATLAS's performance | 3 | 0.41 | 2005 |
| A novel approach for partitioning iteration spaces with variable densities | 5 | 0.45 | 2005 |
| PBExplore: a framework for compiler-in-the-loop exploration of partial bypassing in embedded processors | 12 | 0.78 | 2005 |
| Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures | 5 | 0.57 | 2004 |
| Coordinated parallelizing compiler optimizations and high-level synthesis | 29 | 1.50 | 2004 |
| A geometric approach for partitioning n-dimensional non-rectangular iteration spaces | 8 | 0.53 | 2004 |
| A Data Cache with Dynamic Mapping | 2 | 0.39 | 2003 |
| Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption | 4 | 0.41 | 2002 |
| Processor-memory co-exploration driven by a Memory-Aware Architecture Description Language | 15 | 1.72 | 2001 |
| Fractal Matrix Multiplication: A Case Study on Portability of Cache Performance | 12 | 0.72 | 2001 |
| New directions in compiler technology for embedded systems (embedded tutorial) | 4 | 0.53 | 2001 |
| APEX | 0 | 0.34 | 2001 |
| Compiler-Directed Cache Assist Adaptivity | 5 | 0.50 | 2000 |
| Compiler-Directed Cache Line Size Adaptivity | 6 | 0.65 | 2000 |
| Aggressive Memory-Aware Compilation | 1 | 0.37 | 2000 |
| Customizing Software Toolkits for Embedded Systems-On-Chip | 0 | 0.34 | 2000 |
