Name
Abstract | ||
|---|---|---|
A low-power slew-rate controlled output driver with open loop digital scheme, one-cycle lock time is presented. Proposed output driver maintains slew rate in the range of 2.1V/ns to 3.6V/ns in a one cycle after the enable clock is inserted. It is implemented in 0.18um CMOS process, and the control block consumes 13.7mW at 1Gbps.
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Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ASPDAC.2008.4484070 | ASP-DAC |
Keywords | Field | DocType |
open loop,cmos process,output driver,proposed output driver,one-cycle tuning time,control block consumes,slew rate,low-power slew-rate,one-cycle lock time,digital scheme,detectors,crosstalk,open loop systems,voltage,fpga,phase locked loops,integrated circuit design,signal generators | Computer science,Nanoscale crossbar,Field-programmable gate array,Electronic engineering,Real-time computing,Cmos process,Integrated circuit design,Slew rate,Open-loop controller,Lock time | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4244-1922-7 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Young-Ho Kwak | 1 | 44 | 6.75 |
| Inhwa Jung | 2 | 70 | 11.23 |
| Chulwoo Kim | 3 | 397 | 74.58 |