Name
Abstract | ||
|---|---|---|
We propose a novel energy-efficient memory architecture which relies on the use of cache with a reduced number of tag bits. The idea behind the proposed architecture is based on moving a large number of the tag bits from the cache into an external register (Tag Overflow Buffer) that identifies the current locality of the memory references; additional hardware allows to dynamically update the value of the reference locality contained in the buffer. Energy efficiency is achieved by using, for most of the memory accesses, a reduced-tag cache. This architecture is minimally intrusive for existing designs, since it assumes the use of a regular cache, and does not require any special circuitry internal to the cache such as row or column activation mechanisms. Average energy savings are 51% on tag energy, corresponding to about 20% saving on total cache energy, measured on a set of typical embedded applications. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/DATE.2005.298 | DATE |
Keywords | Field | DocType |
tag energy,novel energy-efficient memory architecture,memory reference,average energy saving,reduced-tag cache,regular cache,tag bit,total cache energy,memory access,energy-efficient cache architecture,tag overflow buffering,energy efficiency,energy efficient,embedded system,set cover,registers,wireless sensor network,circuits,design optimization,embedded systems,coverage,hardware,low power electronics | Cache invalidation,Cache pollution,Computer science,Cache,Parallel computing,Cache-only memory architecture,Page cache,Real-time computing,Cache algorithms,Cache coloring,Computer hardware,Smart Cache | Conference |
ISSN | ISBN | Citations |
1530-1591 | 0-7695-2288-2 | 3 |
PageRank | References | Authors |
0.42 | 16 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mirko Loghi | 1 | 218 | 17.83 |
| Paolo Azzoni | 2 | 30 | 4.18 |
| Massimo Poncino | 3 | 890 | 95.31 |