Name
Abstract | ||
|---|---|---|
Achieving efficient and reliable synchronization is a critical problem in building long systolic arrays. This problem is addressed in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. Analytic bounds are presented for the probability of failure, and an examination is made of the tradeoffs between reliability and throughput in both schemes. The basic conclusion is that as the one-dimensional systolic array gets very long, tree clocking becomes preferable to straight-line clocking. |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1007/BF00925471 | VLSI Signal Processing |
Keywords | DocType | Volume |
Clock Signal,Systolic Array,Clock Period,Clock Pulse,Synchronous System | Journal | 2 |
Issue | ISSN | ISBN |
4 | 1520-6149 | 0-7803-0003-3 |
Citations | PageRank | References |
6 | 0.99 | 8 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. D. Dikaiakos | 1 | 126 | 9.50 |
| Kenneth Steiglitz | 2 | 1128 | 660.13 |