Name
Title | ||
|---|---|---|
A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique |
Abstract | ||
|---|---|---|
In this paper, a burst-mode clock and data recovery (CDR) circuit using a 1/4-rate clock technique is realized for optical communication system. The CDR circuit contains a phase detector and a muxed-oscillator to control the phase of the clocks. In-lock operation is accomplished on the first data transition, and after the first data the clocks are in phase for all data until the data transition is over. The CDR circuit is implemented with 0.18-mum CMOS technology. The experimental results show that the proposed CDR circuit recover the incoming 1.8-Gb/s data |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISCAS.2006.1693274 | ISCAS |
Keywords | Field | DocType |
burst-mode clock recovery circuit,cmos integrated circuits,1.8 gbit/s,phase detector,cmos technology,clocks,data recovery circuit,phase detectors,optical communication,oscillators,optical communication system,0.18 micron,synchronisation,phase control,signal generators,synchronization,oscillations,phase detection,phase locked loops,circuits | Phase-locked loop,Computer science,Clock domain crossing,Burst mode clock and data recovery,Electronic engineering,Synchronous circuit,Clock skew,Phase detector,Digital clock manager,Asynchronous circuit | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-9389-9 | 2 |
PageRank | References | Authors |
0.48 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jun-Hong Weng | 1 | 16 | 3.77 |
| Meng-Ting Tsai | 2 | 25 | 2.61 |
| Jung-Mao Lin | 3 | 28 | 4.52 |
| Ching-Yuan Yang | 4 | 227 | 36.15 |