Name
Title | ||
|---|---|---|
Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration |
Abstract | ||
|---|---|---|
We exploit the inherent information redundancy in the control path of Networks-on-Chip (NoCs) routers to manage transient errors, preventing packet loss and misrouting. Unlike fault-tolerant routing, our method does not drop packets when faults occur in routers and thus does not increase the burden on neighboring routers. Unlike the NoC interconnect links, the routing operation is nonlinear and standard error control coding methods cannot be used. Instead, our method exploits existing information redundancy in the router, significantly reducing the area overhead and power consumption compared to triple-modular redundancy (TMR). An analytical reliability model of our method is provided, including parameters such as circuit size, different error rates for logic gates and registers, and the location of a faulty element. Compared to TMR, the proposed method improves the arbiter reliability by two orders of magnitude while reducing the total power and area by 43% and 64%, respectively. Simulations performed on a 4×4 NoC show that our method reduces the average latency by up to 90% and 12% over no-protection and TMR methods, respectively. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/1999946.1999964 | NOCS |
Keywords | Field | DocType |
packet loss prevention,networks-on-chip,information redundancy,integrated circuit reliability,network routing,tmr method,power consumption,nonlinear routing operation,networks-on-chip routers,analytical reliability model,standard error control coding methods,on-chip interconnect,noc routers,triple-modular redundancy,control path,noc interconnect links,error correction codes,inherent information redundancy,tmr,arbiter,registers,packet loss misrouting,fault-tolerant routing,reliability,area overhead,fault tolerant,transient error management,neighboring routers,logic gates,noc show,network-on-chip,noc routing arbitration,arbiter reliability,transient error,faulty element location,error correction,triple modular redundancy,redundancy,logic gate,error rate,routing,chip,packet loss,network on chip,standard error | Arbiter,Computer science,Parallel computing,Network packet,Packet loss,Computer network,Triple modular redundancy,Network on a chip,Error detection and correction,Real-time computing,Redundancy (engineering),Router | Conference |
ISBN | Citations | PageRank |
978-1-4503-0720-8 | 14 | 0.65 |
References | Authors | |
20 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Qiaoyan Yu | 1 | 174 | 28.58 |
| Meilin Zhang | 2 | 40 | 3.16 |
| Paul Ampadu | 3 | 285 | 28.55 |