Name
Abstract | ||
|---|---|---|
Tapered buffers are widely used in CMOS integrated circuits to drive large capacitive loads. During the design of a tapered buffer, there are several design objectives to consider including delay, area, and power consumption. Existing methods produce suboptimal solutions considering multiple metrics, largely because they decouple different metrics during the design phase, which restricts the solution space for the combined metric. In this paper, a new algorithm is proposed to derive the optimal solution for a unified metric through comprehensive exploration of the solution space. Compared with existing methods, our method yields as high as 18.8% (9.0% on average) improvement in a unified design metric optimizing area, delay, and power simultaneously. The proposed algorithm also reduces buffer power consumption under delay constraints. The power reduction over existing alternatives is as much as 48.1% (28.7% on average). |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISCAS.2011.5938056 | ISCAS |
Keywords | Field | DocType |
cmos integrated circuits,unified design metrics,buffer power consumption reduction,circuit optimisation,low-power electronics,tapered buffer design,delays,large capacitive loads,integrated circuit design,buffer circuits,tapered buffer optimization algorithm,delay constraints,mathematical model,low power electronics,algorithm design and analysis,optimization,algorithm design | Algorithm design,Computer science,CMOS,Capacitive sensing,Electronic engineering,Integrated circuit design,Optimization algorithm,Design objective,Low-power electronics,Power consumption | Conference |
ISSN | ISBN | Citations |
0271-4302 E-ISBN : 978-1-4244-9472-9 | 978-1-4244-9472-9 | 1 |
PageRank | References | Authors |
0.43 | 4 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Song Liu | 1 | 216 | 8.86 |
| Seda Öǧrenci Memik | 2 | 488 | 42.57 |
| Yehea I. Ismail | 3 | 755 | 116.82 |