Name
Abstract | ||
|---|---|---|
The authors analyze a single processor multithreaded architecture using stochastic timed Petri net (STPN) model to study the effects of various parameters such as memory latency and thread runlength, on processor utilization. They first perform a simple analysis of the basic model with constant values for the parameters. This is followed by an extension with stochastic parameters. A detailed simulation study is conducted to validate the analysis. While earlier researchers established that an increase in the number of threads results in increased processor utilization, their results, on the other hand, indicate that average runlength and effective memory latency have stronger impact on processor utilization than the number of threads |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1109/ICCI.1992.227677 | Toronto, Ont. |
Keywords | Field | DocType |
performance evaluation,latency tolerant architectures,memory latency,switches,computer architecture,stochastic processes,computer science,throughput | Architecture,Petri net,Latency (engineering),Computer science,Parallel computing,Thread (computing),CAS latency | Conference |
ISBN | Citations | PageRank |
0-8186-2812-X | 3 | 0.46 |
References | Authors | |
6 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shashank S. Nemawarkar | 1 | 101 | 11.37 |
| Ramaswamy Govindarajan | 2 | 170 | 21.33 |
| Guang R. Gao | 3 | 2661 | 265.87 |
| V. K. Agarwal | 4 | 360 | 44.82 |