Name
Abstract | ||
|---|---|---|
We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) systems. These two algorithms are integrated along with a published floorplanner [5] in a new iterative physical synthesis flow to optimize system throughput and reduce area occupation. The partitioning algorithm performs bottom-up clustering of the internal logic of a given IP core to divide it into smaller ones, each of which has no combinational path from input to output and thus is legal for LI-interface encapsulation. Applying this algorithm to cores on critical feedback loops optimizes their length and in turn enables throughput optimization via the subsequent floorplanning. The merging algorithm reduces the number of cores on non-critical loops, lowering the overall area taken by LI interfaces without hurting the system throughput. Experimental results on a large system-on-chip design show a 16.7% speedup in system throughput and a 2.1% reduction in area occupation. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/DATE.2010.5457005 | DATE |
Keywords | Field | DocType |
local logic structure,iterative physical synthesis flow,optimisation,bottom up clustering,ip core,circuit layout,encapsulation,system throughput,throughput-driven partitioning algorithm,area occupation,local logic structures,high-level physical synthesis,overall area,multi-core soc floorplanning,li interface,li interface encapsulation,system-on-chip,throughput driven partitioning algorithm,multicore soc floorplanning optimization,latency insensitive systems,partitioning algorithm,throughput optimization,throughput preserving merging algorithm,new iterative physical synthesis,computer science,logic gates,clustering algorithms,kernel,merging,stratification,throughput,logic,system on chip,bottom up,feedback loop,law | Logic gate,System on a chip,Computer science,Parallel computing,Real-time computing,Signomial,Throughput,Cluster analysis,Multi-core processor,Floorplan,Speedup | Conference |
ISSN | ISBN | Citations |
1530-1591 | 978-1-4244-7054-9 | 1 |
PageRank | References | Authors |
0.35 | 24 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cheng-Hong Li | 1 | 79 | 5.98 |
| Sampada Sonalkar | 2 | 17 | 1.33 |
| Luca P. Carloni | 3 | 1713 | 120.17 |