Name
Abstract | ||
|---|---|---|
With the advent of dual-core chips in the marketplace, small-scale CMP (chip multiprocessor) architectures are becoming commonplace. We expect a continuing trend of increasing the number of cores on a die to maximize the performance/power efficiency of a single chip. We believe an era of large-scale CMPs (LCMPs) with several tens to hundreds of cores is on the way, but as of now architects have little understanding of how best to build a cache hierarchy given such a large number of cores/threads to support. With this in mind, our initial goals are to prune the cache design space for LCMPs by characterizing basic server workload behavior in such an environment.In this paper, we describe the range of methodologies that we are developing to overcome the challenges of exploring the cache design space for LCMP platforms. We then focus on employing a trace-driven approach to characterizing one key server workload (OLTP) in both a homogeneous and a heterogeneous workload environment. We study the effect of increasing threads (from 1 to 128) on a three-level cache hierarchy with emphasis on second and third level caches. We study the effect of varying sizes at these cache levels and show the effects of threads contending for cache space, the effects of prefetching instruction addresses, and the effects of inclusion. We make initial observations and conclusions about the factors on which LCMP cache hierarchy design decisions should be based and discuss future work. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1145/1105734.1105739 | SIGARCH Computer Architecture News |
Keywords | DocType | Volume |
chip,power efficiency | Journal | 33 |
Issue | Citations | PageRank |
4 | 42 | 1.71 |
References | Authors | |
9 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lisa Hsu | 1 | 746 | 40.78 |
| Ravishankar Iyer | 2 | 720 | 35.52 |
| Srihari Makineni | 3 | 600 | 37.89 |
| Steven K. Reinhardt | 4 | 3885 | 226.69 |
| Don Newell | 5 | 512 | 32.67 |