Name
Abstract | ||
|---|---|---|
We(1) present an approach for experimental metastability characterization of Muller C-elements. It is based on the late transition detection scheme known from flip flop characterization. Substantial additional challenges arise from the facts that with the Muller C-element the input transition to use as a reference for the output delay may change from case to case, and the error flags of the detector need to be reliably synchronized into the other timing domain. Our solution strategy involves taking measurements concurrently and sorting out irrelevant results later on. This is done based on detailed information about type and relative position of input transitions as well as type and polarity of the output transition, for the collection of all of which we propose efficient means. An example study on an FPGA platform proves the applicability and correct operation of our approach. |
Year | Venue | Keywords |
|---|---|---|
2013 | 2013 23RD INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS) | field programmable gate arrays,logic design |
Field | DocType | ISSN |
Logic synthesis,Computer science,Field-programmable gate array,Real-time computing,Sorting,Electronic engineering,Metastability,Flip-flop,Detector | Conference | 2474-5456 |
Citations | PageRank | References |
4 | 0.48 | 5 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Thomas Polzer | 1 | 49 | 8.43 |
| Andreas Steininger | 2 | 308 | 49.17 |