| An Experimental Study of Metastability-Induced Glitching Behavior | 0 | 0.34 | 2019 |
| Refined metastability characterization using a time-to-digital converter. | 1 | 0.39 | 2018 |
| Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA | 0 | 0.34 | 2018 |
| Measuring Metastability with Free-Running Clocks | 1 | 0.37 | 2017 |
| Metastability-Aware Memory-Efficient Time-to-Digital Converters | 1 | 0.37 | 2017 |
| Measuring metastability using a time-to-digital converter | 0 | 0.34 | 2017 |
| A Model for the Metastability Delay of Sequential Elements. | 0 | 0.34 | 2017 |
| On the Appropriate Handling of Metastable Voltages in FPGAs. | 1 | 0.37 | 2016 |
| Measuring the Distribution of Metastable Upsets over Time | 3 | 0.46 | 2015 |
| Containment of Metastable Voltages in FPGAs | 0 | 0.34 | 2015 |
| Enhanced Metastability Characterization Based on AC Analysis | 1 | 0.37 | 2015 |
| Metastability Characterization For Muller C-Elements | 4 | 0.48 | 2013 |
| SET propagation in micropipelines | 2 | 0.46 | 2013 |
| An infrastructure for accurate characterization of single-event transients in digital circuits | 8 | 0.80 | 2013 |
| An Approach for Efficient Metastability Characterization of FPGAs through the Designer | 11 | 0.87 | 2013 |
| Digital Late-Transition Metastability Simulation Model | 1 | 0.37 | 2013 |
| A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding | 3 | 0.43 | 2012 |
| Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip | 5 | 0.55 | 2012 |
| A Metastability-Free Multi-synchronous Communication Scheme for SoCs | 7 | 0.44 | 2009 |
