Name
Title | ||
|---|---|---|
Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types in Embedded VLIW Processors |
Abstract | ||
|---|---|---|
Integrating register allocation and software pipelining of loops is an active research area. We focus on techniques that precondition the dependence graph before software pipelining in order to ensure that no register spill instructions are inserted by the register allocator in the software pipelined loop. If spilling is not necessary for the input code, preconditioning techniques insert dependence arcs so that the maximum register pressure MAXLIVE achieved by any loop schedule is below the number of available registers, without hurting the initiation interval if possible. When a solution exists, a spill-free software pipeline is guaranteed to exist. Existing preconditioning techniques consider one register type (register class) at a time [Deschinkel and Touati 2008]. In this article, we extend preconditioning techniques so that multiple register types are considered simultaneously. First, we generalize the existing theory of register pressure minimization for cyclic scheduling. Second, we implement our method inside the production compiler of the ST2xx VLIW family, and we demonstrate its efficiency on industry benchmarks (FFMPEG, MEDIABENCH, SPEC2000, SPEC2006). We demonstrate a high spill reduction rate without a significant initiation interval loss. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/2043662.2043671 | ACM Trans. Embedded Comput. Syst. |
Keywords | Field | DocType |
vliw processors,register type,preconditioning techniques insert dependence,integrating register allocation,software pipelined loops,register allocator,register pressure minimization,multiple register types,multiple register type,register class,maximum register pressure,register spill instruction,available register,efficient spilling reduction,code optimization,register allocation,software pipelining,instruction level parallelism | Software pipelining,Register allocation,Instruction register,Computer science,Very long instruction word,Parallel computing,Stack register,Control register,Real-time computing,Register window,Processor register,Embedded system | Journal |
Volume | Issue | ISSN |
10 | 4 | 1539-9087 |
Citations | PageRank | References |
2 | 0.38 | 18 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sid-Ahmed-Ali Touati | 1 | 91 | 12.27 |
| Frederic Brault | 2 | 3 | 0.73 |
| Karine Deschinkel | 3 | 15 | 4.02 |
| Benoît Dupont de Dinechin | 4 | 197 | 12.60 |