Name
Abstract | ||
|---|---|---|
For 32/22nm technology nodes and below, double patterning (DP) lithography has become the most promising interim solutions due to the delay in the deployment of next generation lithography (e.g., EUV). DP requires the partitioning of the layout patterns into two different masks, a procedure called layout decomposition. Layout decomposition is a key computational step that is necessary for double patterning technology. Existing works on layout decomposition are all single-threaded, which is not scalable in runtime and/or memory for large industrial layouts. This paper presents the first window-based parallel layout decomposition methods for improving both runtime and memory consumption. Experimental results are promising and show the presented parallel layout decomposition methods obtain upto 21x speedup in runtime and upto 7.5xreduction in peak memory consumption with acceptable solution quality. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1016/j.vlsi.2013.09.002 | Integration |
Keywords | Field | DocType |
double patterning lithography,layout pattern,window-based parallel layout decomposition,next generation lithography,memory consumption,parallel layout decomposition method,scalable parallel layout decomposition,large industrial layout,double patterning technology,layout decomposition,peak memory consumption,double patterning,parallel computing | Integrated circuit layout,Extreme ultraviolet lithography,Computer science,Parallel computing,Electronic engineering,Lithography,Multiple patterning,Next-generation lithography,Scalability,Speedup,Decomposition | Journal |
Volume | Issue | ISSN |
47 | 2 | 0167-9260 |
Citations | PageRank | References |
2 | 0.42 | 26 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei Zhao | 1 | 2 | 0.42 |
| Hailong Yao | 2 | 267 | 39.56 |
| Yici Cai | 3 | 1135 | 120.11 |
| Subarna Sinha | 4 | 198 | 20.80 |
| C. Chiang | 5 | 94 | 11.05 |