Name
Abstract | ||
|---|---|---|
•We evaluate aging effects in flip-flops.•Different flip-flop circuits are evaluated.•Different aging effects (BTI, HCI and TDDB) are taken into account.•FF circuit performances are compared through electrical simulations.•New method of aging analysis in CMOS logic gates is applied. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1016/j.microrel.2013.07.044 | Microelectronics Reliability |
Field | DocType | Volume |
Logic gate,Sequential logic,Propagation delay,FLOPS,CMOS,Electronic engineering,Combinational logic,Time-dependent gate oxide breakdown,Engineering,Transistor,Reliability engineering | Journal | 53 |
Issue | ISSN | Citations |
9 | 0026-2714 | 11 |
PageRank | References | Authors |
0.78 | 12 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cicero Nunes | 1 | 13 | 1.59 |
| Paulo F. Butzen | 2 | 48 | 11.13 |
| André Inácio Reis | 3 | 134 | 21.33 |
| Renato P. Ribas | 4 | 204 | 33.52 |