| A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. | 0 | 0.34 | 2022 |
| maj- $n$ Logic Synthesis for Emerging Technology | 1 | 0.37 | 2020 |
| Parallel Combinational Equivalence Checking | 1 | 0.35 | 2020 |
| Exact Benchmark Circuits for Logic Synthesis | 1 | 0.35 | 2020 |
| Effective Logic Synthesis for Threshold Logic Circuit Design | 1 | 0.37 | 2019 |
| Four-Level Forms for Memristive Material Implication Logic | 1 | 0.37 | 2019 |
| Unlocking Fine-Grain Parallelism for AIG Rewriting | 0 | 0.34 | 2018 |
| A Simple and Effective Heuristic Method for Threshold Logic Identification. | 1 | 0.37 | 2018 |
| SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC. | 0 | 0.34 | 2017 |
| Transistor Count Optimization in IG FinFET Network Design. | 0 | 0.34 | 2017 |
| Graph-Based Transistor Network Generation Method for Supergate Design | 5 | 0.49 | 2016 |
| Threshold Logic Synthesis Based on Cut Pruning | 6 | 0.50 | 2015 |
| Automatic circuit generation for sequential logic debug | 0 | 0.34 | 2015 |
| Factored Forms for Memristive Material Implication Stateful Logic | 3 | 0.45 | 2015 |
| SOP based logic synthesis for memristive IMPLY stateful logic | 4 | 0.43 | 2015 |
| A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design | 3 | 0.44 | 2015 |
| Open Cell Library in 15nm FreePDK Technology. | 41 | 1.70 | 2015 |
| MCML Gate Design for Standard Cell Library | 0 | 0.34 | 2015 |
| Enhanced Spin-Diode Synthesis Using Logic Sharing | 0 | 0.34 | 2015 |
| Bottom-Up Disjoint-Support Decomposition Based On Cofactor And Boolean Difference Analysis | 0 | 0.34 | 2015 |
| Improved logic synthesis for memristive stateful logic using multi-memristor implication | 1 | 0.37 | 2015 |
| Fast buffer delay estimation considering time-dependent dielectric breakdown | 0 | 0.34 | 2015 |
| Deriving reduced transistor count circuits from AIGs | 1 | 0.37 | 2014 |
| Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? | 8 | 0.54 | 2014 |
| Exploring Independent Gates in FinFET-Based Transistor Network Generation | 0 | 0.34 | 2014 |
| A constructive approach for threshold logic circuit synthesis | 0 | 0.34 | 2014 |
| Methodology for achieving best trade-off of area and fault masking coverage in ATMR | 3 | 0.46 | 2014 |
| BTI, HCI and TDDB aging impact in flip-flops. | 11 | 0.78 | 2013 |
| BTI and HCI first-order aging estimation for early use in standard cell technology mapping. | 1 | 0.38 | 2013 |
| A methodology to evaluate the aging impact on flip-flops performance. | 2 | 0.47 | 2013 |
| Power consumption analysis in static CMOS gates | 3 | 0.39 | 2013 |
| Synthesis of threshold logic gates to nanoelectronics | 3 | 0.47 | 2013 |
| Spin diode network synthesis using functional composition. | 1 | 0.38 | 2013 |
| Iterative remapping respecting timing constraints | 0 | 0.34 | 2013 |
| CMOS inverter delay model based on DC transfer curve for slow input. | 0 | 0.34 | 2013 |
| Logic synthesis for manufacturability considering regularity and lithography printability | 0 | 0.34 | 2013 |
| Read-polarity-once Boolean functions | 1 | 0.36 | 2013 |
| Improving the methodology to build non-series-parallel transistor arrangements | 2 | 0.41 | 2013 |
| Analytical logical effort formulation for minimum active area under delay constraints. | 0 | 0.34 | 2013 |
| Parallel prefix adder design using quantum-dot cellular automata. | 0 | 0.34 | 2013 |
| Delay model for static CMOS complex gates. | 0 | 0.34 | 2013 |
| KL-cut based digital circuit remapping | 4 | 0.43 | 2012 |
| Design-oriented delay model for CMOS inverter | 1 | 0.37 | 2012 |
| NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. | 2 | 0.41 | 2012 |
| Functional composition: A new paradigm for performing logic synthesis. | 6 | 0.63 | 2012 |
| Lithography analysis of via-configurable transistor-array fabrics. | 1 | 0.35 | 2012 |
| Design of CMOS logic gates with enhanced robustness against aging degradation. | 8 | 0.59 | 2012 |
| Transistor Sizing Analysis of Regular Fabrics. | 0 | 0.34 | 2011 |
| Impact and optimization of lithography-aware regular layout in digital circuit design | 7 | 0.66 | 2011 |
| Constructive AIG optimization considering input weights | 2 | 0.41 | 2011 |
