Name
Abstract | ||
|---|---|---|
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to facilitate the test generation process and it in turn creates additional constraints for the automatic test pattern generation (ATPG) tool. This paper describes an efficient and effective method to take the hardware restrictions originated from the on-chip clock generators into account in order to avoid generating clock sequences that cannot be produced by hardware. Experimental results on industrial designs show test pattern reduction and/or ATPG run time reduction when compared with the test generation method that enumerates valid clock sequences explicitly and restricts the test generation within enumerated test sequences. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ATS.2009.46 | Asian Test Symposium |
Keywords | Field | DocType |
on-chip clock generator,network synthesis,accurate test clock generation,atpg,test generation method,valid clock,digital phase locked loops,clock sequences,test pattern reduction,test generation process,high performance design,automatic test pattern generation,pll,hardware restrictions,clocks,industrial designs,test generation,clock control,enumerated test sequence,circuit testing,clock sequence,on-chip clock generators,on-chip device plls,system on a chip,generators,force,chip,industrial design,phase locked loops | Phase-locked loop,Automatic test pattern generation,Clock generator,System on a chip,Computer science,Network synthesis filters,Electronic engineering,Real-time computing,Digital clock manager,Test compression,CPU multiplier,Embedded system | Conference |
ISSN | ISBN | Citations |
1081-7735 | 978-0-7695-3864-8 | 8 |
PageRank | References | Authors |
0.68 | 12 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xijiang Lin | 1 | 687 | 42.03 |
| Mark Kassab | 2 | 654 | 48.74 |